Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder
Abstract The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed full adders, using metrics such as power dissipation, propagation delay and power delay product. Comparative performance shows that the proposed 1-bit full adder shows average improvement in terms of power dissipation (31.62 nW and 20.84 nW) and average delay (5.07ns and 11.41ns) over the existing 1-bit hybrid and cell 3 full adder circuit.
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Chen S. L., C. H. Liao, T. K. Chi, T. L. Lin, And C. A. Chen, 2018 “Flexible Signals and Images Lossless Compression Chip Design for IoT and Industry 4.0,” in Proceedings of 14th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications, pp. 1–6. DOI: https://doi.org/10.1109/MESA.2018.8449205
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Badry, O. Al And M. A. Abdelghany, 2018, “Low power 1-Bit full adder using Full-Swing gate diffusion input technique,” in Proceedings of 2018 International Conference on Innovative Trends in Computer Engineering, vol. 2018-March, no. ITCE, pp. 205–208. DOI: https://doi.org/10.1109/ITCE.2018.8316625
Dwivedi, S., K. Khare, And A. K. Dadoria, 2016, “Low-Power High Speed 1-bit Full Adder Circuit Design,” in Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies, pp. 1–5. DOI: https://doi.org/10.1145/2905055.2905321
Kadu C. P., And M. Sharma, 2018, “Area-Improved High-Speed Hybrid 1-bit Full Adder Circuit Using 3T-XNOR Gate,” in Proceedings of International Conference on Computing, Communication, Control and Automation, pp. 1–5. DOI: https://doi.org/10.1109/ICCUBEA.2017.8463827.
Giordani, M., M. Polese, M. Mezzavilla, S. Rangan, And M. Zorzi, 2019 “Towards 6G Networks: Use Cases and Technologies,” IEEE Communications Magazine, vol. 58, no. 3, pp. 55–61, Mar. DOI: https://doi.org/10.1109/MCOM.001.1900411
Wairya, S., R. K. Nagaria, And S. Tiwari, 2012 “Comparative Performance Analysis of XOR- XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design,” International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 2, pp. 432–436, DOI: https://doi.org/10.5121/vlsic.2012.3219
Dokania, V., R. Verma, M. Guduri, And A. Islam, 2018. “Design of 10T full adder cell for ultralow-power applications,” Ain Shams Engineering Journal, vol. 9, no. 4, pp. 2363–2372, DOI: https://doi.org/10.1016/j.asej.2017.05.004
Wairya, S., G. Singh, Vishant, R. K. Nagaria, And S. Tiwari, 2011 “Design analysis of XOR (4T) based low voltage CMOS full adder circuit,” in Proceedings of Nirma University International Conference on Engineering, pp. 1–7. DOI: https://doi.org/10.1109/NUiConE.2011.6153275.
Bhattacharyya, P., B. Kundu, S. Ghosh, V. Kumar, And A. Dandapat, 2015. “Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 10, pp. 2001–2008, DOI: https://doi.org/10.1109/TVLSI.2014.2357057
Goel, S., A. Kumar, And M. A. Bayoumi, 2006. “Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309–1321, DOI: https://doi.org/10.1109/TVLSI.2006.887807
Goel, S., M. A. Elgamel, And M. A. Bayoumi, 2003 “Novel design methodology for high-performance XOR-XNOR circuit design,” in Proceedings of 16th Symposium on Integrated Circuits and Systems Design, pp. 71–76. DOI: https://doi.org/10.1109/SBCCI.2003.1232809
Janwadkar, S. And S. Das, 2018, “Design and Performance Evaluation of Hybrid Full Adder for Extensive PDP Reduction,” in Proceedings of 3rd International Conference for Convergence in Technology, pp. 1–6. DOI: https://doi.org/10.1109/I2CT.2018.8529780
Kandpal, J., A. Tomar, S. Adhikari, and V. Joshi, 2019, “Design of Low Power and High Speed XOR/XNOR Circuit using 90 nm CMOS Technology,” in Proceedings of 2nd International Conference on Innovations in Electronics, Signal Processing and Communication, pp. 221–225. DOI: https://doi.org/10.1109/IESPC.2019.8902392
Hasan, M., U. K. Saha, A. Sorwar, M. A. Z. Dipto, M. S. Hossain, And H. U. Zaman, 2019, “A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic,” in Proceedings of 10th International Conference on Computing, Communication and Networking Technologies, pp. 1–6. DOI: https://doi.org/10.1109/ICCCNT45670.2019.8944888
Hassoune, I., D. Flandre, I. O’connor, And J. D. Legat, 2010. “ULPFA: A new efficient design of a power-aware full adder,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 2066–2074, DOI: https://doi.org/10.1109/TCSI.2008.2001367
Tirumalasetty, V. R., And M. R. Machupalli, “Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications,” International Journal of Electronics, vol. 106, no. 4, pp. 521–536, 2019. DOI: https://doi.org/10.1080/00207217.2018.1545256
Naseri, H., And S. Timarchi, 2018. “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1481–1493, DOI: https://doi.org/10.1109/TVLSI.2018.2820999
Tung, C. K., Y. C. Hung, S. H. Shieh, And G. S. Huang, 2007, “A low-power high-speed hybrid CMOS full adder for embedded system,” in Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 199–202. DOI: https://doi.org/10.1109/DDECS.2007.4295280
Amini-Valashani, M., M. Ayat, And S. Mirzakuchaki, 2017, “Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder,” Microelectronics Journal, vol. 74, pp. 49–59, 2018. DOI: https://doi.org/10.1016/j.mejo.2018.01.018
Abid, Z., H. El-Razouk, And D. A. El-Dib, 2008. “Low power multipliers based on new hybrid full adders,” Microelectronics Journal, vol. 39, no. 12, pp. 1509–1515, DOI: https://doi.org/10.1016/j.mejo.2008.04.002
Sun, Y., And V. Kursun, 2014. “Carbon nanotubes blowing new life into NP dynamic CMOS circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 2, pp. 420–428, DOI: https://doi.org/10.1109/TCSI.2013.2268131
Aguirre-Hernandez, M. And M. Linares-Aranda, 2011 “CMOS Full-Adders for Energy-Efficient Arithmetic Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 718–721. DOI: https://doi.org/10.1109/TVLSI.2009.2038166
Nadu, T., S. Mohan, and N. Rangaswamy, 2014, “Performance Analysis of 1 bit Full Adder Using GDI Logic,” in Proceedings of International Conference on Information Communication and Embedded Systems (ICICES2014), no. 978, pp. 1–4. DOI: https://doi.org/10.1109/ICICES.2014.7034029
Venkatesan, C., M. Thabsera Sulthana, M. G. Sumithra, And M. Suriya, 2019, “Analysis of 1- bit full adder using different techniques in Cadence 45nm Technology,” in Proceedings of 5th International Conference on Advanced Computing and Communication Systems, pp. 179–184. DOI: https://doi.org/10.1109/ICACCS.2019.8728449
Yadav, A. K., B. P. Shrivatava, And A. K. Dadoriya, 2018, “Low power high speed 1-bit full adder circuit design at 45nm CMOS technology,” in Proceedings of International Conference on Recent Innovations in Signal Processing and Embedded Systems, pp. 427–432. DOI: https://doi.org/10.1109/RISE.2017.8378203
Badry, O. Al And M. A. Abdelghany, 2018, “Low power 1-Bit full adder using Full-Swing gate diffusion input technique,” in Proceedings of 2018 International Conference on Innovative Trends in Computer Engineering, vol. 2018-March, no. ITCE, pp. 205–208. DOI: https://doi.org/10.1109/ITCE.2018.8316625
Dwivedi, S., K. Khare, And A. K. Dadoria, 2016, “Low-Power High Speed 1-bit Full Adder Circuit Design,” in Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies, pp. 1–5. DOI: https://doi.org/10.1145/2905055.2905321
Kadu C. P., And M. Sharma, 2018, “Area-Improved High-Speed Hybrid 1-bit Full Adder Circuit Using 3T-XNOR Gate,” in Proceedings of International Conference on Computing, Communication, Control and Automation, pp. 1–5. DOI: https://doi.org/10.1109/ICCUBEA.2017.8463827.
Upadhyay, R. M., Chauhan, R. K., & Kumar, M. (2023). Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder. ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal, 11(4), 475–488. https://doi.org/10.14201/adcaij.28558
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