Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder

  • Rahul Mani Upadhyay
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India rahulmaniupadhyay[at]
  • R. K. Chauhan
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India
  • Manish Kumar
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India


The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed full adders, using metrics such as power dissipation, propagation delay and power delay product. Comparative performance shows that the proposed 1-bit full adder shows average improvement in terms of power dissipation (31.62 nW and 20.84 nW) and average delay (5.07ns and 11.41ns) over the existing 1-bit hybrid and cell 3 full adder circuit.
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