Energy Efficient Compressor Cell for Low Power Computing

  • Rahul Mani Upadhyay
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh rahulmaniupadhyay[at]
  • R. K. Chauhan
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh
  • Manish Kumar
    Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh


As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.
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Akbari, O., Kamal, M., Afzali-Kusha, A., & Pedram, M. 2017. Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 25(4), 1352–1361.

Ansari, M. S., Jiang, H., Cockburn, B. F., & Han, J. 2018. Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8(3), 404–416.

Chang, C. H., Gu, J., & Zhang, M. 2004. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans. Circuits and Syst., 51(10), 1985–1997.

Esposito, D., Strollo, A. G. M., Napoli, E., & Petra, N. 2018. Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits and Syst., 65(12), 4169–4182.

Ha, M., & Lee, S. 2018. Multipliers with Approximate 4-2 Compressors and Error Recovery Modules. IEEE Embedded Systems Letters, 10(1), 6–9.

Kumar, S., & Kumar, M. 2014. 4-2 Compressor design with New XOR-XNOR Module. 4th International Conference on Advanced Computing & Communication Technologies (ACCT), pp. 106–111.

Lee, H., & Sobelman, G. E. 1997. New low-voltage circuits for XOR and XNOR. IEEE Proceedings, Southeastcon, pp. 225–229.

Leon, V., Zervakis, G., Soudris, D., & Pekmestzi, K. 2018. Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 26(3), 421–430.

Momeni, A., Han, J., Montuschi, P., & Lombardi, F. 2015. Design and Analysis of Approximate Compressors for Multiplication. IEEE Trans. Comput., 64(4), pp. 984–994.

Nirlakalla, R., Rao, T. S., & Prasad, T. J. 2011. Performance evaluation of high speed compressors for high speed multipliers. Serbian Journal of Electrical Engineering, 8, 293–306.

Pei, H., Yi, X., Zhou, H., & He, Y. 2020. Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(1), 461–465.

Qian, L., Wang, C., Liu, W., Lombardi, F., & Han, J. 2016. Design and evaluation of an approximate Wallace-Booth multiplier. IEEE Int. Symp. Circuits and Syst. (ISCAS). Montreal, QC, pp. 1974–1977.

Reddy, K. M., Vasantha, M. H., Kumar, Y. N., & Dwivedi, D. 2019. Design and analysis of multiplier using approximate 4-2 compressor. AEU-International Journal of Electronics and Communications, 107, pp. 89–97.

Tonfat, J., & Reis, R. 2012. Low power 3–2 and 4–2 adder compressors implemented using ASTRAN. 3rd IEEE Latin American Symposium on Circuit and Systems (LASCAS), pp. 1–4.

Venkatachalam, S., & Ko., S.-B. 2017. Design of Power and Area Efficient Approximate Multipliers. IEEE Trans. Very Large Scale Integration (VLSI) Systems., 25(5), 1782–1786.

Wang, A., Calhoun, B. H., & Chandrakasan, A. P. 2006. Sub-Threshold Design for Ultra Low-Power Systems, 95. New York, NY, USA: Springer.

Xu, Q., Mytkowicz, T., & Kim, N. S., 2016. Approximate Computing: A Survey. IEEE Design & Test, 33(1), pp. 8–22.

Yang, Z., Han, J., & Lombardi, F. 2015. Approximate compressor for error resilient multiplier design. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 183–186.

Yi, X., Pei, H., Zhang, Z., Zhou, H., & He Y., 2019. Design of an Energy- Efficient Approximate Compressor for Error-Resilient Multiplications. IEEE Int. Symp. Circuits and Syst. (ISCAS). Sapporo, Japan, pp. 1–5.

Zakian, P., & Asli, R. N., 2020. An efficient design of low-power and high-speed approximate compressor in FinFET technology. Computer and Eectrical Engineering, 86, 106651.
Upadhyay, R. M., Chauhan, R. K., & Kumar , M. (2023). Energy Efficient Compressor Cell for Low Power Computing. ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal, 12(1), e30381.


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