Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder

Rahul Mani Upadhyay; R. K. Chauhan; Manish Kumar

doi:10.14201/adcaij.28558

Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder

Rahul Mani Upadhyay

Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India rahulmaniupadhyay[at]gmail.com
R. K. Chauhan

Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India
Manish Kumar

Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India

https://doi.org/10.14201/adcaij.28558

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How to Cite

Upadhyay, R. M., Chauhan, R. K., & Kumar, M. (2023). Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder. ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal, 11(4), 475–488. https://doi.org/10.14201/adcaij.28558

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Editorial dates

Submitted:

27-02-2022

Acceptance:

04-11-2022

Published:

05-06-2023

Issue

Vol. 11 No. 4 (2022)

Section

Articles

Keywords

low power
hybrid full adder
IOT applications
power dissipation
XOR-XNOR circuit

Supporting agencies

This research didn't have any funding

License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.